clang-format
This commit is contained in:
@@ -72,30 +72,27 @@ vaddr_t cputhreads[MAXCPUS];
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* associated with a new cpu. Note that we're not running on the new
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* cpu when this is called.
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*/
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void
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cpu_machdep_init(struct cpu *c)
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{
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vaddr_t stackpointer;
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void cpu_machdep_init(struct cpu *c) {
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vaddr_t stackpointer;
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KASSERT(c->c_number < MAXCPUS);
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KASSERT(c->c_number < MAXCPUS);
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if (c->c_curthread->t_stack == NULL) {
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/* boot cpu; don't need to do anything here */
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}
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else {
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/*
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* Stick the stack in cpustacks[], and thread pointer
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* in cputhreads[].
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*/
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if (c->c_curthread->t_stack == NULL) {
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/* boot cpu; don't need to do anything here */
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} else {
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/*
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* Stick the stack in cpustacks[], and thread pointer
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* in cputhreads[].
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*/
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/* stack base address */
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stackpointer = (vaddr_t) c->c_curthread->t_stack;
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/* since stacks grow down, get the top */
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stackpointer += STACK_SIZE;
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/* stack base address */
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stackpointer = (vaddr_t)c->c_curthread->t_stack;
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/* since stacks grow down, get the top */
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stackpointer += STACK_SIZE;
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cpustacks[c->c_number] = stackpointer;
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cputhreads[c->c_number] = (vaddr_t)c->c_curthread;
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}
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cpustacks[c->c_number] = stackpointer;
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cputhreads[c->c_number] = (vaddr_t)c->c_curthread;
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}
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}
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////////////////////////////////////////////////////////////
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@@ -107,73 +104,61 @@ cpu_machdep_init(struct cpu *c)
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* System/161 processor-ID values.
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*/
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#define SYS161_PRID_ORIG 0x000003ff
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#define SYS161_PRID_2X 0x000000a1
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#define SYS161_PRID_ORIG 0x000003ff
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#define SYS161_PRID_2X 0x000000a1
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static inline
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uint32_t
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cpu_getprid(void)
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{
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uint32_t prid;
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static inline uint32_t cpu_getprid(void) {
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uint32_t prid;
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__asm volatile("mfc0 %0,$15" : "=r" (prid));
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return prid;
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__asm volatile("mfc0 %0,$15" : "=r"(prid));
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return prid;
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}
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static inline
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uint32_t
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cpu_getfeatures(void)
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{
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uint32_t features;
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static inline uint32_t cpu_getfeatures(void) {
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uint32_t features;
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__asm volatile(".set push;" /* save assembler mode */
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".set mips32;" /* allow mips32 instructions */
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"mfc0 %0,$15,1;" /* get cop0 reg 15 sel 1 */
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".set pop" /* restore assembler mode */
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: "=r" (features));
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return features;
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__asm volatile(".set push;" /* save assembler mode */
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".set mips32;" /* allow mips32 instructions */
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"mfc0 %0,$15,1;" /* get cop0 reg 15 sel 1 */
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".set pop" /* restore assembler mode */
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: "=r"(features));
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return features;
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}
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static inline
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uint32_t
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cpu_getifeatures(void)
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{
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uint32_t features;
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static inline uint32_t cpu_getifeatures(void) {
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uint32_t features;
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__asm volatile(".set push;" /* save assembler mode */
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".set mips32;" /* allow mips32 instructions */
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"mfc0 %0,$15,2;" /* get cop0 reg 15 sel 2 */
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".set pop" /* restore assembler mode */
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: "=r" (features));
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return features;
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__asm volatile(".set push;" /* save assembler mode */
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".set mips32;" /* allow mips32 instructions */
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"mfc0 %0,$15,2;" /* get cop0 reg 15 sel 2 */
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".set pop" /* restore assembler mode */
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: "=r"(features));
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return features;
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}
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void
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cpu_identify(char *buf, size_t max)
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{
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uint32_t prid;
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uint32_t features;
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void cpu_identify(char *buf, size_t max) {
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uint32_t prid;
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uint32_t features;
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prid = cpu_getprid();
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switch (prid) {
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case SYS161_PRID_ORIG:
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snprintf(buf, max, "MIPS/161 (System/161 1.x and pre-2.x)");
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break;
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case SYS161_PRID_2X:
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features = cpu_getfeatures();
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snprintf(buf, max, "MIPS/161 (System/161 2.x) features 0x%x",
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features);
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features = cpu_getifeatures();
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if (features != 0) {
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kprintf("WARNING: unknown CPU incompatible features "
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"0x%x\n", features);
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}
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break;
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default:
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snprintf(buf, max, "32-bit MIPS (unknown type, CPU ID 0x%x)",
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prid);
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break;
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}
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prid = cpu_getprid();
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switch (prid) {
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case SYS161_PRID_ORIG:
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snprintf(buf, max, "MIPS/161 (System/161 1.x and pre-2.x)");
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break;
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case SYS161_PRID_2X:
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features = cpu_getfeatures();
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snprintf(buf, max, "MIPS/161 (System/161 2.x) features 0x%x", features);
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features = cpu_getifeatures();
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if (features != 0) {
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kprintf("WARNING: unknown CPU incompatible features "
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"0x%x\n",
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features);
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}
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break;
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default:
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snprintf(buf, max, "32-bit MIPS (unknown type, CPU ID 0x%x)", prid);
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break;
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}
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}
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////////////////////////////////////////////////////////////
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@@ -200,50 +185,43 @@ cpu_identify(char *buf, size_t max)
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* These considerations do not (currently) apply to System/161,
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* however.
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*/
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#define GET_STATUS(x) __asm volatile("mfc0 %0,$12" : "=r" (x))
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#define SET_STATUS(x) __asm volatile("mtc0 %0,$12" :: "r" (x))
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#define GET_STATUS(x) __asm volatile("mfc0 %0,$12" : "=r"(x))
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#define SET_STATUS(x) __asm volatile("mtc0 %0,$12" ::"r"(x))
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/*
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* Interrupts on.
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*/
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void
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cpu_irqon(void)
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{
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uint32_t x;
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void cpu_irqon(void) {
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uint32_t x;
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GET_STATUS(x);
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x |= CST_IEc;
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SET_STATUS(x);
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GET_STATUS(x);
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x |= CST_IEc;
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SET_STATUS(x);
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}
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/*
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* Interrupts off.
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*/
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void
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cpu_irqoff(void)
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{
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uint32_t x;
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void cpu_irqoff(void) {
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uint32_t x;
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GET_STATUS(x);
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x &= ~(uint32_t)CST_IEc;
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SET_STATUS(x);
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GET_STATUS(x);
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x &= ~(uint32_t)CST_IEc;
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SET_STATUS(x);
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}
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/*
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* Used below.
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*/
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static
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void
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cpu_irqonoff(void)
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{
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uint32_t x, xon, xoff;
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static void cpu_irqonoff(void) {
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uint32_t x, xon, xoff;
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GET_STATUS(x);
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xon = x | CST_IEc;
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xoff = x & ~(uint32_t)CST_IEc;
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SET_STATUS(xon);
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__asm volatile("nop; nop; nop; nop");
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SET_STATUS(xoff);
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GET_STATUS(x);
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xon = x | CST_IEc;
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xoff = x & ~(uint32_t)CST_IEc;
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SET_STATUS(xon);
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__asm volatile("nop; nop; nop; nop");
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SET_STATUS(xoff);
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}
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////////////////////////////////////////////////////////////
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@@ -261,49 +239,40 @@ cpu_irqonoff(void)
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* appropriate the mips32 WAIT instruction.
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*/
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static
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inline
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void
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wait(void)
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{
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/*
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* The WAIT instruction goes into powersave mode until an
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* interrupt is trying to occur.
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*
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* Then switch interrupts on and off again, so we actually
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* take the interrupt.
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*
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* Note that the precise behavior of this instruction in the
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* System/161 simulator is partly guesswork. This code may not
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* work on a real mips.
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*/
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__asm volatile(
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".set push;" /* save assembler mode */
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".set mips32;" /* allow MIPS32 instructions */
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".set volatile;" /* avoid unwanted optimization */
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"wait;" /* suspend until interrupted */
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".set pop" /* restore assembler mode */
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);
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static inline void wait(void) {
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/*
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* The WAIT instruction goes into powersave mode until an
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* interrupt is trying to occur.
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*
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* Then switch interrupts on and off again, so we actually
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* take the interrupt.
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*
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* Note that the precise behavior of this instruction in the
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* System/161 simulator is partly guesswork. This code may not
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* work on a real mips.
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*/
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__asm volatile(".set push;" /* save assembler mode */
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".set mips32;" /* allow MIPS32 instructions */
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".set volatile;" /* avoid unwanted optimization */
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"wait;" /* suspend until interrupted */
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".set pop" /* restore assembler mode */
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);
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}
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/*
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* Idle the processor until something happens.
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*/
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void
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cpu_idle(void)
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{
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wait();
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cpu_irqonoff();
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void cpu_idle(void) {
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wait();
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cpu_irqonoff();
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}
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/*
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* Halt the CPU permanently.
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*/
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void
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cpu_halt(void)
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{
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cpu_irqoff();
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while (1) {
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wait();
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}
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void cpu_halt(void) {
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cpu_irqoff();
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while (1) {
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wait();
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}
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}
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